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D a t a S h e e t , V 1 . 0 , Ma y 2 0 0 3
C868
8-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
Edition 2003-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2003. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , V 1 . 0 , Ma y 2 0 0 3
C868
8-Bit Single-Chip Microcontroller
Microcontrollers
Never
stop
thinking.
C868 Revision History: Previous Version: Page 2003-05 V 1.0
Subjects (major changes since last revision) Current data updated Description of I2C included
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8-Bit Single-Chip Microcontroller C800 Family C868
Advance Information
C868
* C800 core : -Fully compatible to standard 8051 microcontroller -Superset of the 8051 architecture with 8 datapointers * 40 MHz internal CPU clock -external clock of 6.67 - 10.67 MHz at 50% duty cycle -300 ns instruction cycle time (@37.5 MHz CPU clock) * 8 Kbyte on-chip Program ROM for C868-1R and 8 KByte on-chip Program RAM for C868-1S * In-system programming support for programming the XRAM(C868-1R) or XRAM/ Program RAM(C868-1S) -This feature is realized through 4KB Boot ROM * 256 byte on-chip RAM * 256 byte on-chip XRAM (further features are on the next page)
RAM 256 x 8
Timer 0 Timer 1
8-bit UART Timer 2
Port 1
XRAM 256 x 8
I/O 5-bit Input 3-bit
CPU 8 datapointers
ROM/RAM 8K x 8
16-bit Capture/ Compare Unit 16-bit Compare Unit
Port 3
I/O 8-bit
Boot ROM 4K x 8
Watchdog Timer
8-Bit ADC
Analog/ Digital Input
Figure 1
Data Sheet
C868 Functional Units
5 V 1.0, 2003-05
C868
* One 8-bit and one 5 bits general purpose push-pull I/O ports - Enhanced sink current of 10 mA on Port 1/3 (total max current of 43 mA @ 100oC) * Three 16-bit timers/counters -Timer 0 / 1 (C501 compatible) -Timer 2 (up/down counter feature) -Timer 1 or 2 can be used for serial baudrate generator * Capture/compare unit for PWM signal generation -3-channel, 16-bit capture/compare unit -1-channel, 16-bit compare unit * Full duplex serial interface (UART) * 5 channel 8-bit A/D Converter - Start of conversion can be synchronized to capture/compare timer 12/13. * 13 interrupt vectors with four priority levels * Programmable 16-bit Watchdog Timer * Brown out detection * Power Saving Modes -Slow-down mode -Idle mode (can be combined with slow-down mode) -Power-down mode with wake up capability through INT0 or RxD pins. * Single power supply of 3.3V, internal voltage regulator for core voltage of 2.5V. * P-DSO-28-1, P-TSSOP-38-1 packages * Temperature ranges: SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868-1RG BA, SAF-C868-1SG BA, SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868A-1RG BA, SAF-C868A-1SG BA, SAF-C868P-1SR BA, SAF-C868P-1SG BA TA = - 40 to 85 oC SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868-1RG BA, SAK-C868-1SG BA, SAK-C868A-1RR BA, SAK-C868A-1SR BA, SAK-C868A-1RG BA, SAK-C868A-1SG BA, SAK-C868P-1SR BA, SAK-C868P-1SG BA TA = - 40 to 125 oC
Data Sheet
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C868
VDDP VSSP
VAREF VAGND
Port 1 5-bit Digital I/O 3-bit Digial Input Port 3 8-bit Digital I/O C868 5 ADC channels
RESET ALE/BSL CTRAP TxD RxD
4 External Interrupts
VDDC
VSSC
Figure 2
Logic Symbol
Data Sheet
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C868
P1.4/RxD P1.3/INT3 P1.2 P1.1/EXF2
1 2 3
38 37 36 35 34 33 32 31
RESET
4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
NC
P1.0/TxD
P3.7/CC60 P3.6/COUT60 NC ALE/BSL
P3.1/CTRAP P3.0/COUT63
NC NC
VDDP VSSP
P3.4/COUT61
XTAL2 XTAL1
C868
30 29 28 27 26 25 24 23 22 21 20
P1.5/CCPOS0/T2/INT0/AN0 P1.6/CCPOS1/T2EX/INT1/AN1 P1.7/CCPOS2/INT2/AN2 VAGND
VAREF
VDDC VSSC
P3.3/CC62 P3.2/COUT62 P3.5/CC61
AN3
AN4
NC NC
NC NC NC NC
Figure 3
C868 Pin Configuration P-TSSOP-38 Package (top view)
P3.4/COUT61
P3.0/COUT63 P3.1/CTRAP
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
XTAL2 XTAL1
ALE/BSL P3.6/COUT60 P3.7/CC60
RESET P1.4/RxD P1.3/INT3 P1.2 P1.1/EXF2 P1.0/TxD VDDP VSSP
VDDC VSSC
P3.3/CC62 P3.2/COUT62 P3.5/CC61 AN4 AN3 VAREF
C868
22 21 20 19 18 17 16 15
VAGND P1.7/CCPOS2/INT2/AN2 P1.6/CCPOS1/T2EX/INT1/AN1 P1.5/CCPOS0/T2/INT0/AN0
Figure 4
C868 Pin Configuration P-DSO-28 Package (top view)
Data Sheet
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C868
Table 1 Symbol
Pin Definitions and Functions Pin Numbers PDSO28 PTSSOP38 6,4-1 11-13 I/O I Port 1 is a combination of 5 bits of push-pull bidirectional I/ O ports and 3 bits of input ports. As alternate digital functions, port 1 contains the interrupt 3, timer 2 overflow flag, receive data input and transmit data output of serial interface. The alternate functions are assigned to the pins of port 1 as follows: P1.0/TxD Transmit data of serial interface P1.1/EXF2 Timer 2 overflow flag P1.2 P1.3/INT3 Interrupt 3 P1.4/RxD Receive data of serial interface, Use as wakeup source from powerdown if bit WS of PMCON0 is set. The input ports are also interrupt ports, input to the timer2, CCU6 modules and ADC: 15 11 I P1.5/Input to Counter 2/External Interrupt 0 Input/ Analog Input Channel 0 External interrupt input or Hall input signal, counter 2 input or input channel 0 to the ADC unit. Use as wakeup source from powerdown if bit WS of PMCON0 is cleared. P1.6/Timer 2 Trigger/External Interrupt 1 Input/ Analog Input Channel 1 External interrupt input or Hall input signal, input channel 1 to the ADC unit, trigger to Timer 2. P1.7/External Interrupt 2 Input/ Analog Input Channel 2 External interrupt input or Hall input signal and input channel 2 to the ADC unit. I/O*) Function
P1.0- P1.4 P1.5P1.7
12-8 15-17
12 11 10 9 8
6 4 3 2 1
16
12
I
17
13
I
*)I=Input O=Output
Data Sheet
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C868
Table 1 Symbol
Pin Definitions and Functions Pin Numbers PDSO28 PTSSOP38 Port 3 is an 8-bit push-pull bidirectional I/O port. This port also serves as alternate functions for the CCU6 functions. The functions are assigned to the pins of port 3 as follows : P3.0/COUT63 16 bit compare channel output P3.1/CTRAP CCU trap input P3.2/COUT62 Output of capture/compare ch 2 P3.3/CC62 Input/output of capture/compare ch 2 P3.4/COUT61 Output of capture/compare ch 1 P3.5/CC61 Input/output of capture/compare ch 1 P3.6/COUT60 Output of capture/compare ch 0 P3.7/CC60 Input/output of capture/compare ch 0 - - I I I Reference voltage for the A/D converter. Reference ground for the A/D converter. Analog Input Channel 4 is input channel 4 to the ADC unit. Analog Input Channel 3 is input channel 3 to the ADC unit. RESET A low level on this pin for two machine cycle while the oscillator is running resets the device. Address Latch Enable/Bootstrap Mode A low level on this pin during reset allows the device to go into the bootstrap mode. After reset, this pin will output the address latch enable signal. The ALE can be disabled by bit EALE in SFR SYSCON0. IO Ground (0V) IO Power Supply (+3.3V) I/O*) Function
P3.0- P3.7
2,3,23, 32,33,25, I/O 24,1, 26,31,24, 22,5,6 36,37
2 3 23 24 1 22 5 6 VAREF VAGND AN4 AN3 RESET 19 18 21 20 7
32 33 25 26 31 24 36 37 15 14 17 16 38
ALE/BSL 4
34
I/O
VSSP VDDP *)I=Input O=Output
14 13
10 9
- -
Data Sheet
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C868
Table 1 Symbol
Pin Definitions and Functions Pin Numbers PDSO28 PTSSOP38 27 28 - O Core Ground (0V) Core Internal Reference (+2.5V) Connect 2*68 - 470nF ceramic capacitor across this pin and core ground. Not connected I/O*) Function
VSSC VDDC
25 26
NC
-
5,7,8,18, - 19,20,21, 22,23,35 29 30 I O
XTAL1 XTAL2
27 28
XTAL1 Output of the inverting oscillator amplifier. XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generation circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected.
*)I=Input O=Output
Data Sheet
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C868
VDDC VSSC XTAL1 XTAL2 PLL
256 x 8 256 x 8
C868
OSC XRAM RAM ROM/ RAM
8k x 8
Boot/ Self Test ROM 4k x 8
RESET
CPU
8 datapointers Port 1 5-bit digital I/O and 3-bit digital input
Programmable Watchdog Timer Timer 0 Timer 1 Timer 2
Port 1
UART Port 3 Capture/Compare Unit 4 external interrupts VAREF VAGND 5-Bit Analog In Port 3 8-bit digital I/O
Interrupt Unit VDDP A/D Converter 8-Bit VSSP
Figure 5
Block Diagram of the C868
Data Sheet
12
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C868
CPU The C868 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 10.67 MHz external crystal (giving a 40MHz CPU clock), 58% of the instructions execute in 300 ns. PSW Program Status Word Register
D7H CY rwh D6H AC rwh D5H F0 rw D4H RS1 rw D3H RS0 rw D2H OV rwh
[Reset value: 00H]
D1H F1 rw D0H P rwh
Field P
Bits 0
Typ Description rwh Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. rw General Purpose Flag rwh Overflow Flag Used by arithmetic instructions. rw Register Bank select control bits These bits are used to select one of the four register banks.
Table 2 : RS1 RS0 Function 0 0 1 1 0 1 0 1 Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH
F1 OV RS0 RS1
1 2 3 4
F0 AC CY
5 6 7
rw
General Purpose Flag
rwh Auxiliary Carry Flag Used by instructions which execute BCD operations. rwh Carry Flag Used by arithmetic instructions.
Data Sheet
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C868
Memory Organization The C868 CPU manipulates operands in the following five address spaces: - up to 8 Kbyte of RAM internal program memory : 8K ROM for C868-1R : 8K RAM for C868-1S - - - - 4 Kbyte of internal Self test and Boot ROM 256 bytes of internal data memory 256 bytes of internal XRAM data memory 128 byte special function register area
Figure 0-1 illustrates the memory address spaces of the C868.
Internal XRAM
FFFFH FF00H
1FFFH indirect addr. Internal RAM direct addr. Special FFH Function Regs. 80H Internal RAM 7FH 00H
Internal Internal Self Test and Boot ROM (4 KByte)
0000H "Data Space"
"Code Space"
"Internal Data Space"
Figure 0-1
C868 Memory Map
Data Sheet
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C868
The various chip modes supported are shown in Figure 6.
Normal Mode
Bootstrap Mode
Normal XRAM Mode
Hardware Software
Bootstrap XRAM Mode
Figure 6
Entry and exit of Chip Modes
A valid hardware reset would, of course, override any of the above entry or exit procedures. Table 0-1 Hardware and Software Selection of Chipmodes Hardware Selection ALE/BSL pin = high RESET rising edge Not possible Software Selection ALE/BSL = don't care; setting bits BSLEN, SWAP = 0,0; execute unlocking sequence setting bits BSLEN,SWAP = 0,1; execute unlocking sequence setting bits BSLEN,SWAP = 1,1; execute unlocking sequence ALE/BSL = don't care; setting bits BSLEN, SWAP = 1,0; execute unlocking sequence
Operating Mode (Chipmode) Normal Mode
Normal XRAM Mode
Bootstrap XRAM Mode Not possible
Bootstrap Mode
ALE/BSL pin = low RESET rising edge
Data Sheet
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C868
Table 3 Chip Mode Normal
Normal Memory Configuration Memory Space Code Space Internal Data Space Memory Boundary ROM/RAM: 0000H to 1FFFH XRAM: FF00H to FFFFH Boot ROM: 0000H to 0FFFH XRAM: FF00H to FFFFH ROM/RAM: 0000H to 1FFFH XRAM: FF00H to FFFFH ROM/RAM: 0000H to 1FFFH Boot ROM: 0000H to 0FFFH XRAM: FF00H to FFFFH ROM/RAM: 0000H to 1FFFH
Bootstrap Code Space Internal Data Space Normal XRAM Code Space Data Space
Bootstrap Code Space XRAM Data Space
Data Sheet
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C868
Bootstrap loader The C868, includes a bootstrap mode, which is activated by setting the ALE/BSL pin at logic low with a pulldown and TxD pin at logic high with a pullup at the rising edge of the RESET. Or it can be entered by software, that is by setting BSLEN bit and resetting SWAP bit in SFR SYSCON1 accompany by an unlock sequence. In the bootstrap mode, software routines of the bootstrap loader located in the boot ROM will be executed. Its purpose is to allow the easy and quick programming of the internal SRAM (0000H to 1FFFH) or XRAM (FF00H to FFFFH) via serial interface (UART) while the MCU is in-circuit. It also provides a way to program SRAM or XRAM through bootstrapping from an external SPI or I2C EEPROM. The first action of the bootstrap loader is to detect the presence of EEPROM and its type, SPI or I2C, and check the first byte of the serial EEPROM. If the first byte is 0A5H, the MCU would enter Phase A to download from the EEPROM. Otherwise, it will enter Phase B to establish a serial communication with the connected host. Bootstrapping from the serial EEPROM can also be done in phase B if it is invoked by the host. Phase B consists of two functional parts that represent two phases: * Phase I: Establish a serial connection and automatically synchronize to the transfer speed (baud rate) of the serial communication partner (host). * Phase II: Perform the serial communication with the host. The host controls the communication by sending special header information, which select one of the working modes. These modes are: Table 4 Modes 0 Serial Communication Modes of Phase B Description Transfer a customer program from the host to the SRAM (0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the beginning of phase II and wait for the next command from the host. Execute a customer program in the XRAM at start address FF00H. Execute a customer program in the SRAM at start address 0000H. Transfer a customer program from the SPI EEPROM to the SRAM (0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the beginning of phase II and wait for the next command from the host. Transfer a customer program from the I2C EEPROM to the SRAM (0000H to 1FFFH) or XRAM (FF00H -FFFFH). Then return to the beginning of phase II and wait for the next command from the host. reserved
1 2 3
4
5-9
The phases of the bootstrap loader are illustrated in Figure 7.
Data Sheet
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C868
Start
Read serial EEPROM (first byte) Yes Phase A Bootstrap from serial EEPROM byte=A5H? No Phase B Init serial interface 0 and synchronize to the host baud rate Receive header block from host Select working mode
Phase B, Phase I
Phase B, Phase II
Activate Mode 4 Load program from I2C serial EEPROM to SRAM/XRAM Activate Mode 3 Load program from SPI serial EEPROM to SRAM/XRAM
Activate mode 0 Load custom code to SRAM/XRAM
Activate Mode 1 Execute custom program in XRAM
Activate Mode 2 Execute custom program in SRAM
Figure 7
The phases of the Bootstrap Loader
The serial communication is activated in phase B. Using a full duplex serial cable (RS232), the MCU must be connected to the serial port of the host computer as shown in Figure 8.
PC Host Computer Serial Interface (asynchronous, 8N1)
Serial Cable full duplex, RS232
C868
Serial Interface, UART Mode 1 (asynchronous, 8N1)
Figure 8
Bootstrap Loader Interface to the PC
Data Sheet
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C868
VC C
VCC
P1.3 P1.1 P1.2 240R
1 6 5 2
/CS SCK SI SO
/HO LD /W P VCC GN D
7 3 8 4
1 6 5 2
A0 A1 A2 GN D
VCC WP SC L SDA
7 3 8 4 3K3 P1.1 P1.2
a) SPI EEPR OM connection
b) I2C EEPRO M connection
Figure 9
EEPROM connections for a) SPI and b) I2C
Data Sheet
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C868
Reset and Brownout The reset input is an active low input. An internal Schmitt trigger is used at the input for noise rejection. The RESET pin must be held low for at least tbd usec. But the CPU will only exit from reset condition after the PLL lock had been detected. During RESET at transition from low to high, C868 will go into normal mode if ALE/BSL is high and bootstrap loading mode if ALE/BSL is low. A pullup to VDDP or pulldown to ground is recommended for pin ALE/BSL. TXD should have a pullup to VDDP and should not be stimulated externally during reset, as a logic low at this pin will cause the chip to go into test mode if ALE/BSL is low. Figure 10 shows the possible reset circuits, note that the RESET pin does not have an internal pullup resistance.
VDDP
a) C868 BA
RESET &
b) C868 BA
RESET
VDDP
c) C868 BA
RESET
Figure 10
Reset Circuitries
An on-chip analog circuit detects brownout, if the core voltage VDDC dips below the threshold voltage VTHRESHOLD momentarily while RESET pin is high. If this detection is active for tbd usec then the device will reset. When VDDC recovers by exceeding VTHRESHOLD while RESET is high, the reset is released once PLL is locked for 4096 clocks. Bit BO in the PMCON0 register is set when brownout detected if brownout detection was enabled, this bit is cleared by hardware reset RESET and software. All ports are tristated during brownout. The VTHRESHOLD has a nominal value of 1.47V, a minimum value of 1.1V and a maximum value of 1.8V.
Data Sheet
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C868
Clock system The C868 clock system consist of the on-chip oscillator, PLL and multiplexer stage. The programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a factor of 1...32 which is specified via CMCON.REL. The system clock is switched from the PLL output to the output from the SDD when slowdown mode is selected.
XTAL1
PLL On-Chip Osc
fOSC
clkin
clkout
fPLL
SDD
MUX system clock (fSYS)
XTAL2
Figure 11
Block Diagram of the Clock Generation
Data Sheet
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C868
The PLL output frequency is determined by:
fPLL = fVCO / K =
The range for the VCO frequency is given by: 100 MHz fVCO 160 MHz
15 x fOSC K
[1]
[2]
The relationship between the input frequency and VCO frequency is given by:
fVCO = 15 x fOSC
This gives the range for the input frequency which is given by: 6.67 MHz fOSC 10.67 MHz
[3]
[4]
Table 5
Output Frequencies fPLL Derived from Various Output Factors fPLL fVCO = fVCO = 100 MHz 160 MHz 50 25 20 16.67 12.5 11.11 10 6.25 80 40 32 26.67 20 17.78 16 10 Duty Jitter Cycle [%] 50 50 40 50 50 44 50 50 linear depending on fVCO at fVCO =100MHz: +/-300ps at fVCO =160MHz: +/-250ps additional jitter for odd Kdiv factors tbd.
K-Factor Selected KDIV Factor 2 4 51) 6 8 91) 10 16
1)
000B 010B 011B 100B 101B 110B 111B 001B
These odd factors should not be used (not tested because off the unsymmetrical duty cycle). Shaded combinations should not be used because they are above the maximum CPU frequency of 40MHz.
2)
Data Sheet
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C868
Figure 12 shows the recommended oscillator circuitries for crystal and external clock operation.
Crystal Oscillator Mode
XTAL2
Driving from External Source External Oscillator Signal
XTAL2
6.67-10.67 MHz
C868
XTAL1
N.C.
XTAL1
C = 20 pF 10 pF for crystal operation (incl. StrayCapacitance)
Figure 12
Recommended Oscillator Circuit
In this application the on-chip oscillator is used as a crystal-controlled, positivereactance oscillator (a more detailed schematic is given in Figure 13). lt is operated in its fundamental response mode as an inductive reactor in parallel resonance with a capacitor external to the chip. The crystal specifications and capacitances are noncritical. In this circuit tbd pF can be used as single capacitance at any frequency together with a good quality crystal. A ceramic resonator can be used in place of the crystal in cost-critical applications. If a ceramic resonator is used, the two capacitors normally have different values depending on the oscillator frequency. We recommend consulting the manufacturer of the ceramic resonator for value specifications of these capacitors.
Data Sheet
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C868
To internal timing circuitry
XTAL1 *)
XTAL2
C868
C1
C2
*) Crystal or ceramic resonator
Figure 13
On-Chip Oscillator Circuitry
To drive the C868 with an external clock source, the external clock signal has to be applied to XTAL2, as shown in Figure 14. XTAL1 has to be left unconnected. A pullup resistor is suggested (to increase the noise margin), but is optional if VOH of the driving gate corresponds to the VIH2 specification of XTAL2.
VDDC
N.C.
C868 XTAL1
External Clock Signal
XTAL2
Figure 14
External Clock Source
Data Sheet
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C868
0.1
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. For accessing the mapped special function area, bit RMAP in special function register SYSCON0 must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared ("0"). SYSCON0 System Control Register 0
7 r 6 r 5 EALE rw 4 RMAP rw 3 r
[Reset value: XX10XXX1B]
2 r 1 r 0 XMAP0 rw
The functions of the shaded bits are not described here
Field
RMAP
Bits 4
Typ Description rw
Special Function Register Map Control RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled.
-
[7:2]
r
reserved; returns '0' if read; should be written with '0';
As long as bit RMAP is set, the mapped special function register area can be accessed. This bit is not cleared automatically by hardware. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. The 109 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. All available SFRs whose address bits 0-2 are 0 (e.g. 80H, 88H, 90H, ..., F0H, F8H ) are bit- addressable. Totally there are 128 directly addressable bits within the SFR area. All SFRs are listed in Table 6 and Table 7.In Table 6 they are organized in groups which refer to the functional blocks of the C868-1R, C868-1S. Table 7 illustrates the contents (bits) of the SFRs
Data Sheet
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C868
Table 6
Special Function Registers - Functional Blocks Name Add- Contents ress after Reset E0H1) F0H1) 83H 82H 84H D0H1) 81H 98H1) 99H A8H1) A9H AAH B8H1) ACH 88H1) 89H 8AH 8BH 8CH 8DH 87H 8EH 8FH 91H 92H 93H E8H1) F8H1) C0H1) F9H ADH AFH 00H 00H 00H 00H 00H 00H 07H 00H 00H 0X000000B2) XXXXX000B2) XX0000XXB2) XX000000B2) XX000000B2) 00H 00H 00H 00H 00H 00H 0XXX0000B 2) XXX00000B2) 10011111B XXXXXX00B2) XXXXXX00B2) XX0000X0B2) XXXXX000B2) XXXXX000B2) X0X00000B2) 00H XX10XXX1B2) 00XXX0X0B2)
Block Symbol
C800 ACC core B DPH DPL DPSEL PSW SP SCON SBUF IEN0 IEN1 IEN2 IP0 IP1 TCON TMOD TL0 TL1 TH0 TH1 PCON System PMCON0 CMCON EXICON IRCON0 IRCON1 PMCON1 PMCON2 SCUWDT VERSION SYSCON0 SYSCON1
Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer Serial Channel Control Register Serial Data Buffer Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 interrupt Priority Register 1 Timer 0/1 Control Register Timer Mode Register Timer 0, Low Byte Timer 1, Low Byte Timer 0, High Byte Timer 1, High Byte Power Control Register Wake-up Control Register Clock Control Register External Interrupt Control Register External Interrupt Request Register Peripheral Interrupt Request Register Peripheral Management Ctrl Register Peripheral Management Status Register SCU/Watchdog Control Register ROM Version Register System Control Register 0 System Control Register 1
1) Bit-addressable special function registers 2) "X" means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
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C868
Table 6
Special Function Registers - Functional Blocks (cont'd) Name Add- Contents ress after Reset D8H1) 00H D9H XX000000B2) DBH 00H 90H1) FFH 90H1) FFH B0H1) FFH B0H1) FFH B1H 00H B4H XXX00X00B2) A2H A3H B2H B3H C8H1) C9H CBH CAH CDH CCH XXXXXX00B2) 00H 00H 00H 00H XXXXXXX0B2) 00H 00H 00H 00H
Block Symbol
A/D- ADCON0 Con- ADCON1 verter ADDATH Ports P1 4) P1DIR 3) P3 4) P3DIR 3) P3ALT P1ALT Watch WDTCON dog WDTREL WDTL WDTH Timer T2CON 2 T2MOD RC2H RC2L T2H T2L
A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register Port 1 Register Port 1 Direction Register Port 3 Register Port 3 Direction Register Port 3 Alternate Function Register Port 1 Alternate Function Register Watchdog Timer Control Register Watchdog Timer Reload Register Watchdog Timer, Low Byte Watchdog Timer, High Byte Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload/Capture, High Byte Timer 2 Reload/Capture, Low Byte Timer 2, High Byte Timer 2, Low Byte
1) Bit-addressable special function registers 2) "X" means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
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Table 6
Special Function Registers - Functional Blocks (cont'd) Name Add- Contents ress after Reset ECH EDH EEH EFH DEH DFH D2H D3H C2H C3H C4H C5H C6H C7H D4H D5H E6H E7H F4H F5H EAH EBH E2H E3H F2H F2H F3H E4H E5H BBH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0H 00H 00H 00H 00H
Block Symbol
Capture/ Compare Unit
T12L T12H T13L T13H T12PRL T12PRH T13PRL T13PRH CC60RL CC60RH CC61RL CC61RH CC62RL CC62RH CC63RL CC63RH T12DTCL T12DTCH CMPSTATL CMPSTATH CMPMODIFL CMPMODIFH TCTR0L TCTR0H TCTR2L3) TCTR4L4) TCTR4H4) ISL ISH PISELH
Timer T12 Counter Register, Low Byte Timer T12 Counter Register, High Byte Timer T13 Counter Register, Low Byte Timer T13 Counter Register, High Byte Timer T12 Period Register, Low Byte Timer T12 Period Register, High Byte Timer T13 Period Register, Low Byte Timer T13 Period Register, High Byte Capture/Compare Ch 0 Reg, Low Byte Capture/Compare Ch 0 Reg, High Byte Capture/Compare Ch 1 Reg, Low Byte Capture/Compare Ch 1 Reg, High Byte Capture/Compare Ch 2 Reg, Low Byte Capture/Compare Ch 2 Reg, High Byte T13 Compare Register, Low Byte T13 Compare Register, High Byte Timer T12 Dead Time Ctrl, Low Byte Timer T12 Dead Time Ctrl, High Byte Compare Timer Status, Low Byte Compare Timer Status, High Byte Compare Timer Modification, Low Byte Compare Timer Modification, High Byte Timer Control Register 0, Low Byte Timer Control Register 0, High Byte Timer Control Register 2, Low Byte Timer Control Register 4, Low Byte Timer Control Register 4, High Byte Cap/Com Interrupt Register, Low Byte Cap/Com Interrupt Register, High Byte Port Input Selector Register, High Byte
1) Bit-addressable special function registers 2) "X" means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
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Table 6
Special Function Registers - Functional Blocks (cont'd) Name Add- Contents ress after Reset BCH BDH BCH BDH BEH BFH BEH BFH FAH FBH FCH FDH FEH FFH B6H B7H D6H D7H CEH CFH A6H DCH DDH DCH DDH D6H F6H F7H 00H 00H 00H 00H 40H 39H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H
Block Symbol
Capture/ Compare Unit
ISSL3) ISSH3) ISRL4) ISRH4) INPL3) INPH3) IENL4) IENH4) CC60SRL CC60SRH CC61SRL CC61SRH CC62SRL CC62SRH CC63SRL CC63SRH MODCTRL3) MODCTRH3) TRPCTRL TRPCTRH PSLRL MCMOUTL3) MCMOUTH3) MCMOUTSL4) MCMOUTSH4) MCMCTRLL4) T12MSELL T12MSELH
Cap/Com Int Status Set Reg, Low Byte Cap/Com Int Status Set Reg, High Byte Cap/Com Int Status Reset Reg, Low Byte Cap/Com Int Status Reset Reg,High Byte Cap/Com Int Node Ptr Reg, Low Byte Cap/Com Int Node Ptr Reg, High Byte Cap/Com Interrupt Register, Low Byte Cap/Com Interrupt Register, High Byte Cap/Com Channel 0 Shadow, Low Byte Cap/Com Channel 0 Shadow, High Byte Cap/Com Channel 1 Shadow, Low Byte Cap/Com Channel 1 Shadow, High Byte Cap/Com Channel 2 Shadow, Low Byte Cap/Com Channel 2 Shadow, High Byte T13 Compare Shadow Reg, Low Byte T13 Compare Shadow Reg, High Byte Modulation Control Register, Low Byte Modulation Control Register, High Byte Trap Control Register, Low Byte Trap Control Register, High Byte Passive State Level Register, Low Byte MCM Output Register, Low Byte MCM Output Register, High Byte MCM Output Shadow Register, Low Byte MCM Output Shadow Register,High Byte MCM Control Register, Low Byte T12 Cap/Com Mode Sel Reg, Low Byte T12 Cap/Com Mode Sel Reg, High Byte
1) Bit-addressable special function registers 2) "X" means that the value is undefined and the location is reserved 3) Register is mapped by bit RMAP in SYSCON0.4=1 4) Register is mapped by bit RMAP in SYSCON0.4=0
Data Sheet
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Table 7 Addr Register 81H 82H 83H 84H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH SP DPL DPH
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7 .7 .7 .7 -
Bit 6 .6 .6 .6 -
Bit 5 .5 .5 .5 - - TF0
Bit 4 .4 .4 .4 - SD TR0
Bit 3 .3 .3 .3 - GF1 IE1
Bit 2 .2 .2 .2 D2 GF0 IT1
Bit 1 .1 .1 .1 D1 PDE IE0
Bit 0 .0 .0 .0 D0 IDLE IT0
07H 00H 00H
DPSE 00H L
PCON 0XX0 SMOD - 0000B TCON 00H TMOD 00H TL0 TL1 TH0 TH1 00H 00H 00H 00H TF1 TR1
GATE C/NT1 M1(1) M0(1) GATE C/NT0 M1(0) M0(0) 1 0 .7 .7 .7 .7 .6 .6 .6 .6 - .5 .5 .5 .5 - .4 .4 .4 .4 EBO .3 .3 .3 .3 BO REL3 .3 .3 - - INP1 TB8 .3 .2 .2 .2 .2 .1 .1 .1 .1 .0 .0 .0 .0 EPWD REL0 .0 .0
PMCO XXX0 - N0 0000B
SDST WS AT REL2 .2 .2 - - INP0 RB8 .2 REL1 .1 .1
CMCO 1001 KDIV2 KDIV1 KDIV0 REL4 N 1111B FFH .7 .7 .6 .6 - - - SM1 .6 .5 .5 - - INP3 SM2 .5 .4 .4 - - INP2 REN .4 P1DIR FFH
90H2) P1 90H 91H 92H 93H 98H 99H
3)
EXICO XXXX - N XX00B IRCO N0 IRCO N1 XXXX - XX00B XX00 - 00X0B SM0 .7
ESEL3 ESEL2 EXINT EXINT 3 2 - TI .1 IADC RI .0
SCON 00H SBUF 00H
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Table 7 Addr Register A2H A3H A6H A8H A9H AAH ACH ADH AFH
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7
Bit 6 - .6
Bit 5 - .5 PSL5 ET2 -
Bit 4 - .4 PSL4 ES -
Bit 3 - .3 PSL3 ET1 -
Bit 2 - .2 PSL2 EX1 EX3
Bit 1 - .1 PSL1 ET0 EX2
Bit 0 WDTI N .0 PSL0 EX0 EADC - .0 XMAP 0 SWAP .0 .0
WDTC XXXX - ON XX00B WDTR 00H EL PSLRL 00H IEN0 IEN1 IEN2 IP1 .7
PSL63 - - - - -
0X00 EA 0000B XXXX - X000B XX00 - 00XXB XX00 - 0000B
EINP3 EINP2 EINP1 EINP0 - .5 .4 .3 .2 - .1 -
SYSC XX10 - - ON0 XXX1B SYSC 00XX ESWC SWC ON1 X0X0B FFH .7 .7 CC60 .7 .7 .6 .6
EALE RMAP - _ .5 .5 _ .4 .4 _ .3 .3
BSLE _ N .2 .2 .1 .1
B0H2) P3
B0H3) P3DIR FFH B1H P3ALT 00H B2H B3H B4H B6H B7H WDTL 00H WDTH 00H
COUT CC61 60 .6 .6 _ .6 .6 .5 .5 _ .5 .5
COUT CC62 61 .4 .4 RxD .4 .4 .3 .3 INT3 .3 .3
COUT CTRA COUT 62 P 63 .2 .2 _ .2 .2 .1 .1 EXF2 .1 .1 .0 .0 TxD .0 .0
P1ALT XXX0 _ 0X00B CC63 00H SRL CC63 00H SRH .7 .7
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Table 7 Addr Register B8H BBH IP0
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7
Bit 6 - -
Bit 5 .5
Bit 4 .4
Bit 3 .3
Bit 2 .2
Bit 1 .1
Bit 0 .0
XX00 - 0000B -
PISEL 00H H 00H 00H 00H 00H 00H 00H 00H 00H
ISPOS ISPOS ISPOS ISPOS ISPOS ISPOS 2.1 2.0 1.1 1.0 0.1 0.0
BCH3) ISSL BCH2) ISRL BDH3) ISSH BDH2) ISRH BEH2) IENL BEH3) INPL BFH2) IENH BFH3) INPH C0H C2H C3H C4H C5H
ST12P ST12O SCC62 SCC62 SCC61 SCC61 SCC60 SCC60 M M F R F R F R RT12P RT12O RCC6 RCC6 RCC6 RCC6 RCC6 RCC6 M M 2F 2R 1F 1R 0F 0R - - SIDLE SWHE SCHE - RIDLE RWHE RCHE - STRP ST13P ST13C F M M RTRP RT13P RT13C F M M
ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R INPCH INPCH INPCC INPCC INPCC INPCC INPCC INPCC E.1 E.0 62.1 62.0 61.1 61.0 60.1 60.0 - - - .7 .7 .7 .7 ENIDL ENWH ENCH - E E E - PLLR .6 .6 .6 .6 ENTR ENT13 ENT13 PF PM CM
INPT1 INPT1 INPT1 INPT1 INPER INPER 3.1 3.0 2.1 2.0 R.1 R.0 - .5 .5 .5 .5 WDTR WDTE WDTD WDTR WDTR OI IS S E .4 .4 .4 .4 .3 .3 .3 .3 .2 .2 .2 .2 .1 .1 .1 .1 .0 .0 .0 .0
SCUW 00H DT CC60 00H RL CC60 00H RH CC61 00H RL CC61 00H RH
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Table 7 Addr Register C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D2H D3H D4H D5H
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7 .7 .7 TF2
Bit 6 .6 .6 EXF2 - .6 .6 .6 .6 -
Bit 5 .5 .5
Bit 4 .4 .4
Bit 3 .3 .3
Bit 2 .2 .2
Bit 1 .1 .1 C/T2 - .1 .1 .1 .1
Bit 0 .0 .0 CP/ RL2 DCEN .0 .0 .0 .0
CC62 00H RL CC62 00H RH T2CO 00H N
RCLK TCLK EXEN TR2 2 - .5 .5 .5 .5 - - .4 .4 .4 .4 - - .3 .3 .3 .3 - - .2 .2 .2 .2
T2MO XXXX - D XXX0B RC2L 00H RC2H 00H TL2 00H TH2 00H TRPC 00H TRL TRPC 00H TRH PSW 00H T13PR 00H L T13PR 00H H CC63 00H RL CC63 00H RH .7 .7 .7 .7 -
TRPM TRPM TRPM 2 1 0
TRPP TRPE TRPE TRPE TRPE TRPE TRPE TRPE EN N13 N5 N4 N3 N2 N1 N0 CY .7 .7 .7 .7 - AC .6 .6 .6 .6 - F0 .5 .5 .5 .5 RS1 .4 .4 .4 .4 RS0 .3 .3 .3 .3 OV .2 .2 .2 .2 F1 .1 .1 .1 .1 P .0 .0 .0 .0
D6H2) MCMC 00H TRLL D6H3) MODC 00H TRL
SWSY SWSY - N1 N0
SWSE SWSE SWSE L2 L1 L0
MCME - N
T12M T12M T12M T12M T12M T12M ODEN ODEN ODEN ODEN ODEN ODEN 5 4 3 2 1 0
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Table 7 Addr Register
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D7H3) MODC 00H TRH D8H D9H DBH ADCO 00H N0
ECT13 - O
T13M T13M T13M T13M T13M T13M ODEN ODEN ODEN ODEN ODEN ODEN 5 4 3 2 1 0
ADST ADBS ADM1 ADM0 CCU- ADCH ADCH ADCH Y ADEX 2 1 0 - .6 R ADST ADST ADST ADCT ADCT ADCT C2 C1 C0 C2 C1 C0 .5 .4 .3 .2 .1 .0
ADCO XX00 - N1 0000B ADDA 00H TH .7 -
DCH3) MCMO 00H UTL DCH2) MCMO 00H UTSL DDH3) MCMO 00H UTH DDH2) MCMO 00H UTSH DEH DFH E0H E2H E3H E4H E5H T12PR 00H L T12PR 00H H ACC 00H TCTR 00H 0L TCTR 10H 0H ISL ISH 00H 00H
MCMP MCMP MCMP MCMP MCMP MCMP 5 4 3 2 1 0 MCMP MCMP MCMP MCMP MCMP MCMP S5 S4 S3 S2 S1 S0 CURH CURH CURH EXPH EXPH EXPH 2 1 0 2 1 0 CURH CURH CURH EXPH EXPH EXPH S2 S1 S0 S2 S1 S0 .5 .5 .5 .4 .4 .4 .3 .3 .3 .2 .2 .2 .1 .1 .1 .0 .0 .0
STRM - CM - -
STRH - P .7 .7 .7 CTM - .6 .6 .6 CDIR -
STE12 T12R STE13 T13R
T12PR T12CL T12CL T12CL E K2 K1 K0 T13PR T13CL T13CL T13CL E K2 K1 K0
T12PM T12O M - IDLE
ICC62 ICC62 ICC61 ICC61 ICC60 ICC60 F R F R F R WHE CHE TRPS TRPF T13PM T13C M
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Table 7 Addr Register E6H E7H E8H EAH EBH ECH EDH EEH EFH F0H
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7
Bit 6 -
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T12DT 00H CL T12DT 00H CH -
DTM5 DTM4 DTM3 DTM2 DTM1 DTM0 DTE2 DTE1 DTE0
DTR2 DTR1 DTR0 - - - - - - .4 .4 .4 .4 .4 - - - - .3 .3 .3 .3 .3
PMCO XXXX - N1 X000B CMPM 00H ODIFL CMPM 00H ODIFH T12L T12H T13L T13H B 00H 00H 00H 00H 00H - - .7 .7 .7 .7 .7
CCUDI T2DIS ADCDI S S MCC6 MCC6 MCC6 2S 1S 0S MCC6 MCC6 MCC6 2R 1R 0R .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0
MCC6 - 3S MCC6 - 3R .6 .6 .6 .6 .6 .5 .5 .5 .5 .5
F2H2) TCTR 00H 4L F2H3) TCTR 00H 2L F3H2) TCTR 00H 4H F4H F5H F6H F7H CMPS 00H TATL CMPS 00H TATH T12M 00H SELL T12M 00H SELH
T12ST T12ST - D R -
DTRE T12RE T12RS T12RR S S
T13TE T13TE T13TE T13TE T13TE T13SS T12SS D1 D0 C2 C1 C0 C C - - - - T13RE T13RS T13RR S CC62S CC61S CC60S T T T
T13ST T13ST - D R - CC63S - T
T13IM COUT COUT CC62P COUT CC61P COUT CC60P 63PS 62PS S 61PS S 60PS S MSEL MSEL MSEL MSEL MSEL MSEL MSEL MSEL 613 612 611 610 603 602 601 600 - - - - MSEL MSEL MSEL MSEL 623 622 621 620
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Table 7 Addr Register F8H F9H FAH FBH FCH FDH FEH FFH
Contents of the SFRs, SFRs in numeric order of their addresses
Content after Reset1)
Bit 7
Bit 6 -
Bit 5 -
Bit 4 -
Bit 3 -
Bit 2
Bit 1
Bit 0 ADCS T
PMCO XXXX - N2 X000B VERSI 00H ON CC60 00H RL CC60 00H RH CC61 00H RL CC61 00H RH CC62 00H RL CC62 00H RH
CCUS T2ST T
PROT VER6 VER5 VER4 VER3 VER2 VER1 VER0 .7 .7 .7 .7 .7 .7 .6 .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 .3 .3 .3 .3 .3 .3 .2 .2 .2 .2 .2 .2 .1 .1 .1 .1 .1 .1 .0 .0 .0 .0 .0 .0
1) X means that the value is undefined and the location is reserved 2) This register is mapped with RMAP (SYSCON0.4)=0 3) This register is mapped with RMAP (SYSCON0.4)=1 Shaded registers are bit-addressable special function registers
Data Sheet
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Ports The C868 has two kinds of ports. The first kind is push-pull ports instead of the traditional quasi-bidirectional ports. The ports belonging to this kind are lsb of port 1 which is a 5bit I/O port and port 3 which is an eight-bit I/O port. When configured as inputs, these ports will be high impedance with Schmitt trigger feature. Port 3 is alternate for capture/ compare functions whereas, port 1 has alternate functions for some of the pins. The second kind is input ports which are shared by msb of port 1 which is a 3-bit input port, the interrupts, timer 2 inputs, capture/compare hall inputs and analog inputs.
Data Sheet
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Timer 0 and 1 Timer 0 and 1 can be used in four operating modes as listed in Table 8: Table 8 Mode 0 1 2 3 Timer 0 and 1 Operating Modes Description 8-bit timer with a divide-by-32 prescaler 16-bit timer 8-bit timer with 8-bit autoreload TMOD M1 0 0 1 M0 0 1 0 1 System Clock
fSYS/(12*32) fSYS/12
Timer 0 used as one 8-bit timer and one 8-bit 1 timer timer 1 stops
The register is incremented every machine cycle. Since the machine cycle consist of twelve oscillator periods, the count rate is 1/12th of the system frequency. External inputs INT0 and INT1 can be programmed to function as a gate to facilitate pulse width measurements. Figure 15 illustrates the input clock logic.
fSYS / 12 C/T = 0 Timer 0/1 Input Clock
Control TR0
&
=1
Gate
1
INT0
Pin
Figure 15
Data Sheet
Timer 0 and 1 Input Clock Logic
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Timer/Counter 2 with Compare/Capture/Capture Timer 2 is a 16-bit timer/counter with an up/down count feature. It has three operating modes: * 16-bit auto-reload mode (up or down counting) * 16-bit capture mode * Baudrate generator Table 9 Mode Timer/Counter 2 Operating Modes T2CON RCLK CP/ or RL2 TCLK 16-bit Autoreload 0 0 0 0 16-bit Capture 0 0 0 0 0 1 TR2 T2MOD T2CON DCEN EXEN T2EX Remarks System Clock Inte- T2 rnal X reload upon overflow reload trigger (falling edge) 0 1 X down counting up counting 16-bit Timer/ Counter (only up-counting) capture T2H,T2L-> RC2H,RC2L X no overflow interrupt request(TF2) extra external interrupt ("Timer 2") X Timer 2 stops -
1 X 1 1 1
0 0 1 1 X
0 1 X X 0
fSYS max /12 fSYS
/24
fSYS max /12 fSYS
/24
0
1
1
X
1
Baudrate 1 Generator 1
X
1
X
0
fSYS /2
X
1
X
1
off Note:
X
X
0
X
X
denotes a falling edge
Data Sheet
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Serial Interface (UART) The serial port is a full duplex port capable of simultaneous transmit and receive functions. It is also receive-buffered; it can commence reception of a second byte before a previously-received byte has been read from the receive register. The serial port can operate in 3 modes as illustrated in Table 10. Table 10 Mode 0 1 2 3 UART Operating Modes SCON SM1 0 0 1 1 SM0 0 1 0 1 Reserved 8-bit UART, variable baudrate 10 bits are transmitted (through TxD) or received (RxD) 9-bit UART, fixed baudrate 11 bits are transmitted (through TxD) or received (RxD) 9-bit UART, variable baudrate Similar to mode 2, except for the variable baudrate. Description
For clarification, some terms regarding the difference between "baudrate clock" and "baudrate" should be mentioned. The serial interface requires a clock rate which is 16 times the baudrate for internal synchronization. Therefore, the baudrate generators must provide a "baudrate clock" to the serial interface which divides it by 16, thereby resulting in the actual "baudrate".
Data Sheet
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The baudrates in Mode 1 and 3 are determined by the timer overflow rate. These baudrates can be determined by Timer 1 or by Timer 2 or both (one for transmit, the other for receive. Table 11 Serial Interface - Baud Rate Dependencies Active Control Bits Baud Rate Calculation TCLK/ RCLK 0 1 Mode 2 (9-bit UART)
1)
Serial Interface Operating Modes Mode 1 (8-bit UART) Mode 3 (9-bit UART)
SMOD x x 0 1 Controlled by timer 1 overflow: (2SMOD x Timer 1 overflow rate) / 32 Controlled by baud rate generator (2SMOD x Timer 21) overflow rate) / 32
-
fSYS / 64 fSYS / 32
Timer 2 functioning as baudrate generator
Data Sheet
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Capture/Compare Unit (CCU6) The CCU6 provides two independent timers (T12, T13), which can be used for PWM generation, especially for AC-motor control. Additionally, special control modes for block commutation and multi-phase machines are supported. Timer 12 Features * Three capture/compare channels, each channel can be used either as capture or as compare channel. * Generation of a three-phase PWM supported (six outputs, individual signals for highside and lowside switches) * 16 bit resolution, maximum count frequency = system clock * Dead-time control for each channel to avoid short-circuits in the power stage * Concurrent update of the required T12/13 registers * Center-aligned and edge-aligned PWM can be generated * Single-shot mode supported * Many interrupt request sources * Hysteresis-like control mode Timer 13 Features * * * * * One independent compare channel with one output 16 bit resolution, maximum count frequency = system clock Can be synchronized to T12 Interrupt generation at period-match and compare-match Single-shot mode supported
Additional Features * * * * * * * * Block commutation for Brushless DC-drives implemented Position detection via Hall-sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fast emergency stop without CPU load via external signal (CTRAP) Control modes for multi-channel AC-drives Output levels can be selected and adapted to the power stage Capture/compare unit can be powerdown in normal, idle and slow-down modes
The timer T12 can work in capture and/or compare mode for its three channels. The modes can also be combined. The timer T13 can work in compare mode only. The multichannel control unit generates output patterns which can be modulated by T12 and/or T13. The modulation sources can be selected and combined for the signal modulation.
Data Sheet
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Switching Examples
T12clk T12P T12P-1 T12P-2 compare-match = period-match zero-match 1 0 0 1 < T12P-3 active T12 shadow transfer 0 0 1 T12P passive 0 0 T12P active 0 CDIR STE12 CC6x compare state T12P-1 T12P-2 compare-match = period-match zero-match 1 T12 T12P
T12 shadow transfer
Figure 16
Edge-aligned mode with duty cycles near 100% and near 0%. Applicable to T13 as well.
T12clk compare-match 2 1 0 1 1 1 active 0 0 2 passive T12 shadow transfer active T12 shadow transfer 1 1 1 1 2 2 1 0 0 0 0 CDIR STE12 CC6x compare state 1 compare-match 2 T12
Figure 17
Data Sheet
Centre-aligned mode with duty cycles near 100% and near 0%.
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Dead-time Generation The dead-time generation logic is built in a similar way for all three channels of T12. Each of the three channels works independently with its own dead-time counter and the trigger and enable signals.
T12
Centre-aligned
T12 Edge-aligned
CC6xST CC6xST DTCx_o COUT6x (CC6xPS=0) CC6x (CC6xPS=0)
Figure 18
Dead-time generation for centre and edge aligned modes
Capture Mode In capture mode the bits CC6xST indicate the occurrence of the selected capture event according to the bit fields MSEL6x. A rising and/or a falling edge on the pins CC6x can be selected as capture event, that is used to transfer the contents of timer T12 to the CC6xR and CC6xSR registers. In order to work in capture mode, the capture pins have to be configured as inputs.
Data Sheet
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Single Shot Mode In single shot mode, the timer T12 stops automatically at the end of the its counting period.
edge-aligned mode T12P T12P-1 T12P-2 2 1 0 T12 T12R CC6xST if T12SSC = '1' 0 T12 T12R CC6xST one-match while counting down period-match while counting up center-aligned mode
if T12SSC = '1'
Figure 19
Single Shot Mode of T12, T13 is edge-aligned mode only.
Hysteresis-Like Control Mode The hysteresis-like control mode (MSEL6x = '1001') offers the possibility to switch off the PWM output if the input CCPOSx becomes '0'. This can be used as a simple motor control feature by using a comparator indicating e.g. over current.
T12
COUT6x CC6x CCPOSx
Figure 20
Data Sheet
Hysteresis-like control mode
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Synchronization of T13 to T12 The timer T13 can be synchronized on a T12 event. Combined with the single shot mode, this feature can be used to generate a programmable delay after a T12 event.
5 compare-match while counting up T12 0 2 T13 T13R 1 0 2 1 4 3
Synchronization of T13 to T12 Multi-channel Mode The multi-channel mode offers a possibility to modulate all six T12-related output signals within one instruction. The bits in bit field MCMP are used to select the outputs that may become active. If the multi-channel mode is enabled (bit MCMEN='1'), only those outputs may become active, which have a '1' at the corresponding bit position in bit field MCMP. This bit field has its own shadow bit field MCMPS, which can be written by SW. The transfer of the new value in MCMPS to the bit field MCMP can be triggered by and synchronized to T12 or T13 events. This structure permits the SW to write the new value, which is then taken into account by the HW at a well-defined moment and synchronized to a PWM period. This avoids unintended pulses due to unsynchronized modulation sources (T12, T13, SW).
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Trap Handling The trap functionality permits the PWM outputs to react on the state of the input pin CTRAP. This functionality can be used to switch off the power devices if the trap input becomes active (e.g. as emergency stop).
T12
T13
TRPF TRPS TRPS TRPS
CTRAP active sync. to T13 sync. to T12 no sync.
Figure 21
Trap State Synchronization (with TRM2='0')
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Modulation control The modulation control part combines the different modulation sources, six T12-related signals from the three compare channels, the T13-related signal and the multi-channel modulation signals. each modulation source can be individually enabled for each output line. Furthermore, the trap functionality is taken into account to disable the modulation of the corresponding output line during the trap state (if enabled).
T13
CC60 (MCMP0, no modulation) COUT60 (MCMP1, no modulation)
CC60 (T12, no modulation)
COUT60 (T12, no modulation) CC60 (MCMP0 modulated with T12) COUT60 (MCMP1 modulated with T12)
CC60 (MCMP0 modulated with T12 and 13) COUT60 (MCMP1 modulated with T12 and T13)
Figure 22
Modulation Control example for CC60 and COUT60.
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Hall Sensor Mode In Brushless-DC motors the next multi-channel state values depend on the pattern of the Hall inputs. There is a strong correlation between the Hall pattern (CURH) and the modulation pattern (MCMP). Because of different machine types the modulation pattern for driving the motor can be different. Therefore it is wishful to have a wide flexibility in defining the correlation between the Hall pattern and the corresponding modulation pattern. The CCU6 offers this by having a register which contains the actual Hall pattern (CURHS), the next expected Hall pattern (EXPHS) and its output pattern (MCMPS). At every correct Hall event (CHE, see figure Hall Event Actions) a new Hall pattern with its corresponding output pattern can be loaded (from a predefined table) by software into the register MCMOUTS. Loading this shadow register can also be done by a write action on MCMOUTS with bit STRHP = '1' The sampling of the Hall pattern (on CCPOSx) is done with the T12 clock. By using the dead-time counter DTC0 (mode MSEL6x= '1000') a hardware noise filter can be implemented to suppress spikes on the Hall inputs due to high di/dt in rugged inverter environment. In case of a Hall event the DTC0 is reloaded and starts counting. When the counter value of one is reached, the CCPOSx inputs are sampled (without noise and spikes) and are compared to the current Hall pattern (CURH) and to the expected Hall pattern (EXPH). If the sampled pattern equals to the current pattern the edge on CCPOSx was due to a noise spike and no action will be triggered (implicit noise filter). If the sampled pattern equals to the next expected pattern the edge on CCPOSx was a correct Hall event, the bit CHE is set which causes an interrupt and the resets T12 (for speed measurement, see description mode '1000' below). This correct Hall event can be used as a transfer request event for register MCMOUTS. The transfer from MCMOUTS to MCMOUT transfers the new CURH-pattern as well as the next EXPH-pattern. In case of the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set which also can cause an interrupt and sets the IDLE mode clearing MCMP (modulation outputs are inactive). To restart from IDLE the transfer request of MCMOUTS have to be initiated by software (bit STRHP and bitfields SWSEL/SWSYN).
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Below is a table listing output (MCMP) for a BLDC motor. Block Commutation Control Table Mode CCPOS0CCPOS2 Inputs CCP CCP CCP CC60 OS0 OS1 OS2 Rotate left, 1 0 phase shift 1 1 0 0 0 Rotate right 1 1 1 0 0 0 Slow down Idle1)
1)
CC60 - CC62 Outputs CC61 CC62
COUT60 - COUT62 Outputs COUT6 COUT6 COUT6 0 1 2 inactive active active inactive inactive inactive inactive inactive
0 0 1 1 1 0 1 0 0 0 1 1 X X
1 0 0 0 1 1 0 0 1 1 1 0 X X
inactive inactive active inactive inactive active inactive active inactive active active active active active
inactive active
inactive inactive inactive active inactive inactive
inactive inactive inactive inactive active inactive inactive inactive active inactive inactive inactive active
inactive inactive inactive inactive active inactive inactive inactive active inactive active active inactive inactive inactive inactive inactive active active
inactive active inactive active
inactive inactive active inactive inactive active
inactive active
X X
inactive inactive inactive active
inactive inactive inactive inactive inactive inactive
In case of the sampled Hall inputs were neither the current nor the expected Hall pattern, the bit WHE (wrong Hall event) is set which also can cause an interrupt and sets the IDLE mode clearing MCMP (modulation outputs are inactive).
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For Brushless-DC motors there is a special mode (MSEL6x = '1000b') which is triggered by a change of the Hall-inputs (CCPOSx). This mode shows the capabilities of the CCU6. Here T12's channel 0 acts in capture function, channel 1 and 2 in compare function (without output modulation) and the multi-channel-block is used to trigger the output switching together with a possible modulation of T13. After the detection of a valid Hall edge the T12 count value is captured to channel 0 (representing the actual motor speed) and resets the T12. When the timer reaches the compare value in channel 1, the next multi-channel state is switched by triggering the shadow transfer of bit field MCMP (if enabled in bit field SWEN). This trigger event can be combined with several conditions which are necessary to implement a noise filtering (correct Hall event) and to synchronize the next multi-channel state to the modulation sources (avoiding spikes on the output lines). This compare function of channel 1 can be used as a phase delay for the position input to the output switching which is necessary if a sensorless back-EMF technique is used instead of Hall sensors. The compare value in channel 2 can be used as a time-out trigger (interrupt) indicating that the motors destination speed is far below the desired value which can be caused by a abnormal load change. In this mode the modulation of T12 has to be disabled (T12MODENx = '0').
CC60
act. speed
CC61
phase delay
ch0 gets captured value for act. speed
ch2 compare for timeout
CC62
timeout capture event resets T12 1 0 1 1 0 0 1 1 0 0 1 0 0 1 1 ch1 compare for phase delay
CCPOS0 CCPOS1 CCPOS2 CC6x COUT6y
0 0 1
Figure 0-2
Timer T12 Brushless-DC Mode (MSEL6x = 1000)
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A/D Converter The C868 includes a high performance / high speed 8-bit A/D-Converter (ADC) with 5 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: - - - - - - - 5 multiplexed input channels, which can also be used as digital inputs 8-bit resolution with TUE of +/- 2 LSB8. Single or continuous conversion mode Start of conversion by software and hardware Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Powerdown in normal, idle and slow-down modes
The ADC supports two conversion modes - single and continuous conversions. For each mode, there are two ways in which conversion can be started - by software and by the T13PM signal from the CCU module. Writing a `0' to bit CCU_ADEX select conversion control by ADST. Writing a '1' to bit field ADST starts conversion on the channel that is specified by ADCH. In single conversion mode, bit field ADM is cleared to '0'. This is the default mode selected after hardware reset. When a conversion is started, the channel specified is sampled. The busy flag ADBSY is set and ADST is cleared. When the conversion is completed, the interrupt request signal ADCIRQ is asserted possitively for 2 clocks and the 8-bit result together with the number of the converted channel is transferred to the result register ADDATH. In continuous conversion mode, bit field ADM is set to '1'. In this mode, the ADC repeatedly converts the channel specified by ADCH. Bit ADST is cleared at the beginning of the first conversion. The busy flag ADBSY is asserted until the last conversion is completed. At the end of each conversion, the interrupt request signal ADCIRQ will be activated. To stop conversion, ADM has to be reset by software. If the channel number ADCH is changed while continuous conversion is in progress, the new channel specified will be sampled in the conversions that follow. A new request to start conversion will be allowed only after the completion of any conversion that is in progress. Writing a `1' to bit CCU_ADEX select conversion control by T13PM trigger signal from the CCU module. Note: Caution must be taken when changing conversion start source. To change conversion source from software to hardware trigger, it is best to let remaining software conversion to complete before changing. To change conversion source from hardware trigger to software, it is best to change source first, let any
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remaining hardware conversion to complete before beginning a software conversion. Conversion and sample time control The conversion and sample times are programmed via the bit fields ADCTC and ADSTC respectively of the register ADCON1. Bit field ADCTC (conversion time control) selects the internal ADC clock - adc_clk. Bit field ADSTC (sample time control) selects the sample time. The total A/D conversion time is given by: tADCC = 2/fSYS + tS + 8/adc_clk [5]
The sample time tS is configured in periods of the selected internal ADC clock. The table below lists the possible combinations.
ADCTC
Clock Divider (TVC) 28 24 20 16 12 8 4
ADC Basic Clock adc_clk fSYS / 32 fSYS / 28 fSYS / 24 fSYS / 20 fSYS / 16 fSYS / 12 fSYS / 8 fSYS / 4
ADSTC
Sample Time tS (Periods of adc_clk, STC) 4 6 8 10 12 14 16
000 (default) 32 001 010 011 100 101 110 111
000 (default) 2 001 010 011 100 101 110 111
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Interrupt System The C868 provides 13 interrupt vectors with four priority levels. Nine interrupt requests are generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial channel, A/D converter, and the capture/compare unit with 4 interrupts) and four interrupts may be triggered externally. The wake-up from power-down mode interrupt has a special functionality which allows the software power-down mode to be terminated by a short negative pulse at pins CCPOS0/T2/INT0/AN0 or P1.4/RxD. The 13 interrupt sources are divided into six groups. Each group can be programmed to one of the four interrupt priority levels. Additionally, 4 of these interrupt sources are channeled from 7 Capture/Compare (CCU6) interrupt sources. Figure 23 to Figure 28 give a general overview of the interrupt sources and illustrate the request and control flags.
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ICC60R P3.7/ CC0 ISL.0 ICC60F ISL.1 ICC61R P3.5/ CC1 ISL.2 ICC61F ISL.3 ICC62R P3.3/ CC2 ISL.4 ICC62F ISL.5 T12 One Match T12OM ISL.6 T12 Period Match T13 Compare Match T13 Period Match P3.1/ CTRAP T12PM ISL.7 T13CM ISH.0 T13PM ISH.1 TRPF ISH.2 Wrong Hall Event WHE ISH.5 ENTRPF IENH.2 ENWHE IENH.5 ENT13CM IENH.0 ENT13PM IENH.1 ENT12OM IENL.6 ENT12PM IENL.7 ENCC62R IENL.4 ENCC62F IENL.5 ENCC61R IENL.2 ENCC61F IENL.3 ENCC60R IENL.0 ENCC60F IENL.1
1
INPL.1 INPL.0
1
INPL.3 INPL.2
1
INPL.5 INPL.4
1
INPH.3 INPH.2
1
INPH.5 INPH.4
1
INPH.1 INPH.0
Correct Hall Event
CHE ISH.4
ENCHE IENH.4 INPL.7 INPL.6 Capcom Interrupt node 0 Capcom Interrupt node 1 Capcom Interrupt node 2 Capcom Interrupt node 3
Figure 23
Capture/Compare module interrupt structure
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Highest Priority Level INT0_ CORE_N (CCPOS / IT0 T2 / INT0 / TCON.0 AN0) IE0 TCON.1 EX0 IEN0.0 0003H Lowest Priority Level
A/D Converter
IADC IRCON1.0
EADC
0033H
IEN1.0
IP1.0
IP0.0
Timer 0 Overflow
TF0 TCON.5 ET0 IEN0.1 000BH
P o l l i n g S e q u e n c
CCPOS2 / INT2 / AN2 ESEL2 EXICON.0
EX2 IRCON0.0 EX2 IEN1.1 003BH
EA Bit addressable Request flag is cleared by hardware IEN0.7
IP1.1
IP0.1
Figure 24
Interrupt Structure, Overview Part 1
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Priority Level Highest CCPOS1 / T2EX / INT1 / AN1 IE1 IT1 TCON.2 TCON.3 EX1 IEN0.2 0013H Lowest Priority Level
P1.3 / INT3 ESEL3 EXICON.1
EXINT3 IRCON0.1 EX3 IEN1.2 0043H
Capture/compare interrupt node 0
INP0 IRCON1.2
EINP0 IEN2.2
0083H
P o l l i n g S e q u e n c
EA IEN0.7 Bit addressable Request flag is cleared by hardware
IP1.2
IP0.2
Figure 25
Interrupt Structure, Overview Part 2
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Highest Priority Level
Lowest Priority Level
Timer 1 Overflow
TF1 TCON.7 ET1 IEN0.3 001BH
Capture/compare interrupt node 1
INP1 IRCON1.3
EINP1 IEN2.3
008BH
P o l l i n g S e q u e n c
EA IEN0.7 Bit addressable Request flag is cleared by hardware
IP1.3
IP0.3
Figure 26
Interrupt Structure, Overview Part 3
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Highest Priority Level
Priority Level
RI UART SCON.0 TI SCON.1
1 ES IEN0.4 0023H
Capture/compare interrupt node 2
INP2 IRCON1.4
EINP2 IEN2.4
0093H
P o l l i n g S e q u e n c
EA Bit addressable Request flag is cleared by hardware IEN0.7
IP1.4
IP0.4
Figure 27
Interrupt Structure, Overview Part 4
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Highest Priority Level Timer 2 Overflow
TF2 IRCON0.6 ET2 IEN0.5 002BH Priority Level
Capture/compare interrupt node 3
INP3 IRCON1.5
EINP3 IEN2.5
009BH
P o l l i n g S e q u e n c
EA IEN0.7 Bit addressable Request flag is cleared by hardware
IP1.5
IP0.5
Figure 28
Interrupt Structure, Overview Part 5
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Table 12
Interrupt Source and Vectors Interrupt Vector Address(core connections) 0003H(EX0) 000BH(ET0) 0013H(EX1) 001BH(ET1) 0023H(ES) 002BH(EX5) 0033H(EX6) 003BH(EX7) 0043H(EX8) 004BH(EX9) 0053H(EX10) 005BH(EX11) 0063H(EX12) 006BH(EX13) Interrupt Request Flags
Interrupt Source
External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow A/D Converter External Interrupt 2 External Interrupt 3
IE0 TF0 IE1 TF1 RI / TI TF2 IADC IEX2 IEX3
CAPCOM interrupt node 0 CAPCOM interrupt node 1 CAPCOM interrupt node 2 CAPCOM interrupt node3
0083H(EX14) 008BH(EX15) 0093H(EX16) 009BH(EX17) 00A3H(EX18) 00ABH(EX19) 00D3H(EX20) 00DBH(EX21) 00E3H(EX22)
INP01) INP11) INP21) INP31)
Wake-up from power-down mode
1)
007BH
-
Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/compare ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F. The other flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE.
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lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure determined by the polling sequence. This is illustrated in Table 13 . Table 13 Interrupt Source Structure Interrupt Source Priority High Priority Priority EXINT0 TF0 EXINT1 TF1 RI + TI TF2 IADC EXINT2 EXINT3 INP01) INP11) INP21) INP31) Low Low High Priority
Interrupt Priority Bits Group of Interrupt Group 0 1 2 3 4 5
1)
IP0.0 IP0.1 IP0.2 IP0.3 IP0.4 IP0.5
Capture/compare has 10 interrupt sources channeled to the 4 interrupt nodes INP0..3. The 3 capture/ compare ports has 3 pairs of interrupt request flags, ICC60R, ICC60F, ICC61R, ICC61F, ICC62R, ICC62F. The other flags are T12OM, T12PM, T13CM, T13PM, TRPF, WHE, CHE.
Within a column, the topmost interrupt is serviced first, then the second and the third, when available. The interrupt groups are serviced from left to right of the table. A lowpriority interrupt can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same or a lower priority. An interrupt of the highest priority level cannot be interrupted by another interrupt source.
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Fail Save Mechanisms The C868 offers enhanced fail save mechanisms, which allow an automatic recovery from software upset or hardware failure : a programmable watchdog timer (WDT), with variable time-out period from 12.8s to 819.2s at fSYS = 40 MHz. Programmable Watchdog Timer To protect the system against software failure, the user's program has to clear this watchdog within a previously programmed time period. lf the software fails to do this periodical refresh of the watchdog timer, an internal reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. lt also times out if a software error is based on hardware-related problems. The watchdog timer in the C868 is a 16-bit timer, which is incremented by a count rate of fSYS/2 upto fSYS/128. The machine clock of the C868 is divided by a prescaler, a divideby-two or a divide-by-128 prescaler. The upper 8 bits of the Watchdog Timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits are reset on each service access. Figure 29 shows the block diagram of the watchdog timer unit.
WDT Control
WDTREL
1:2
Clear MUX WDT Low Byte WDT High Byte WDTRST
fSYS
1:128
DISWDT
WDTIN
Figure 29
Block Diagram of the Programmable Watchdog Timer
After a reset, the Watchdog Timer is automatically enabled. If it is disabled, it cannot be enabled again during active mode of the device. If the software fails to clear the watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTR in SCUWDT is set). A refresh of the watchdog timer is done by setting bits WDTRE and WDTRS (in
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SFR SCUWDT) consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power-down mode of the processor (see section "Power Saving Modes"). It is not possible to use the idle mode in combination with the watchdog timer function. Therefore, even the watchdog timer cannot reset the device when one of the power saving modes has been entered accidentally. The time period for an overflow of the Watchdog Timer is programmable in two ways : - the input frequency to the Watchdog Timer can be selected via bit WDTIN in register WDTCON to be either fSYS/2 or fSYS/128. - the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON. The period PWDT between servicing the Watchdog Timer and the next overflow can therefore be determined by the following formula: [0.1]
PWDT = 2(1 +WDTIN*6) * (216 - WDTREL * 2 8)
fSYS
Table 14 lists the possible ranges for the watchdog time which can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 14 Watchdog Time Ranges Reload value in WDTREL Prescaler for fSYS 2 (WDTIN = `0') 40 MHz FFH 7FH 00H 12.8 s 20 MHz 25.6 s 16 MHz 32.0 s 4.13 ms 128 (WDTIN = `1') 40 MHz 20 MHz 16 MHz 819.2 s 1.64 ms 2.05 ms 105.7 ms 211.3 ms 264 ms
1.65 ms 3.3 ms
3.28 ms 6.55 ms 8.19 ms 209.7 ms 419.4 ms 524 ms
For safety reasons, the user is advised to rewrite WDTCON each time before the Watchdog Timer is serviced.
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Power Saving Modes The C868 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can also be used for further power reduction in idle mode. * Idle Mode In the idle mode, the oscillator of the C868 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial port, the A/D converter, the capture/compare unit, and all timers are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode. * Slow Down Mode In some applications, where power consumption and dissipation are critical, the controller might run for a certain time at reduced speed (for example, if the controller is waiting for an input signal). Since in CMOS devices, there is an almost linear dependence of the operating frequency and the power supply current, so, a reduction of the operating frequency results in reduced power consumption. * Software Power Down Mode In the software power down mode, the on-chip oscillator which operates with the XTAL pins and the PLL are all stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's. The port pins which serve the alternate output functions show the values they had at the end of the last cycle of the instruction which initiated the power down mode. ALE is held at logic low level or high impedance if disabled. In the power down mode of operation, VDDP can be reduced to minimize power consumption. It must be ensured, however, that VDDP is not reduced before the power down mode is invoked, and that VDDP is restored to its normal operating level before the power down mode is terminated.
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Table 15 Mode Idle Mode
Power Saving Modes Overview Entering ORL PCON,#01H Leaving by Occurance of any enabled interrupt Hardware Reset Remarks CPU clock is stopped; CPU maintains its data; peripheral units are active (if enabled) and provided with clock Internal clock rate is reduced to a configurable factor of 1 /2 to 1/32 of the system clock rate CPU clock is stopped; CPU maintains all its data; Peripheral units are active (if enabled) and provided with a configurable factor of 1/ to 1/ of the 2 32 system clock rate
Slow Down Mode
In normal mode: ORL PCON,#10H
ANL PCON,#0EFH or Hardware Reset
With idle mode: ORL PCON,#11H
Occurance of any enabled interrupt to exit idle mode and the instruction ANL PCON,#0EFH to terminate slow down mode Hardware Reset
Software Power Down mode
With external wake-up capability from power down enabled ORL PMCON0,#01H (to wake-up via pin INT0) or ORL PMCON0,#03H (to wake-up via pin RxD) ORL PCON,#02H
Oscillator is stopped; When INT0 or RxD Contents of on-chip goes low for at least RAM and SFR's are 10 s (latch phase). maintained But it is desired that the corresponding pin must be held at high level during the power down mode entry and up to the wake-up. Hardware Reset
Hardware Reset
With external wake-up capability from power down disabled ORL PCON,#02H
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Device Specifications Absolute Maximum Ratings Absolute Maximum Rating Parameters Parameter Ambient temperature under bias Symbol -40 -65 -0.3 -0.5 Limit Values min. max. 125 150 4.6 4.6 C C V V Unit Notes
TA Storage temperature TSTG Voltage on VDDP pins with respect VDDP VIN0
to ground (VSSP) Voltage on any pin except int/ analog and XTAL with respect to ground (VSSP)
Voltage on any int/analog pin with VIN1 respect to ground (VSSP) Voltage on XTAL pins with respect to ground (VSSC) Input current on any pin during overload condition
-0.5 -0.5 -10 -
4.6 4.6 10 43 tbd
V V mA mA W
-1) -
VIN2
OV
Absolute sum of all input currents |OV| during overload condition Power dissipation
1)
PDISS
Proper operation is not guaranteed if overload conditions occur on functional pins like XTAL2 etc.
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN>VDDP or VINVDDC or VIN2Data Sheet
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Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C868. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Operating Condition Parameters Parameter Symbol 3.0 tbd Digital ground voltages Ambient temperature Analog reference voltage Analog ground voltage Analog input voltage External Clock Input current on any pin during overload condition except int/ analog and XTAL int/analog pin XTAL pin Absolute sum of all input currents during overload condition Notes:
1) 2)
Limit Values min. max. 3.6 3.6 0 -40 -40 3.0V 85 125
Unit Notes V V V C C V V V mA Active mode,
Digital supply voltage VDDP
fSYSmax = 40 MHz
PowerDown mode1) SAF-C868... SAK-C868... -2)3)
VSSC,VSSP TA VAREF VAGND VAIN fOSC
OV0
VDDP +
0.1
VSSP - 0.1 VSSP +
0.1
VAGND
6.67 -5
VAREF
10.67 5
MHz -
OV1 OV2 OV
-2 -5 -
5 5 |20|
mA mA mA
-3)4) -3)5) -3)
Oscillator or external clock disabled. Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDDP +0.5V or VOV < VSSP -0.5V). The absolute sum of input currents on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits. Not 100% tested, but guaranteed by design characterization.
3)
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4)
Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > tbd or VOV < VSSC -0.5V). The absolute sum of input currents on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits. Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDDC +0.5V or VOV < VSSC -0.5V). The absolute sum of input currents on all port pins may not exceed 20mA. The suply voltages VDDP and VSSP must remain within the specified limits.
5)
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DC Characteristics (Operating Conditions apply) Parameter Input low voltages all except XTAL2, int/analog int/analog XTAL2 Input high voltages all except XTAL2, int/analog int/analog XTAL2 Output low voltage Symbol Limit Values min. max. -1) 0.3VDDP 0.3VDDC 0.1VDDC V V V - Unit Test Condition
VIL0 VIL1 VIL2 VIH0 VIH1 VIH2 VOL
-0.5 -0.5 -0.5
0.7VDDP VDDP+0.5 V 0.7VDDC VDDP+0.5 V 0.7VDDC VDDC+0.5 V - - 0.45 0.55 - 0.5 0.5 10 2.75 470 10 V V V uA uA uA V nF pF SAF-C868... IOL=10mA SAK-C868... IOL=10mA IOH=10mA 0.4Output high voltage Input leakage current (all except int/analog) Input leakage current (int/ analog) Input low current (XTAL2) Digital supply voltage Blocking capacitor for VDDC Pin capacitance Note:
1)
VOH ILI0 ILI1 ILI2 VDDC CIO
2.4 - - - 2.253) 136 -
fC = 1MHz TA= 250C
Interrupt/analog pins are input only and has CMOS characteristics whereas the other I/O pins have TTL characteristics. The leakage current of interrupt/analog pins depends on the leakage current of the CMOS pad for the digital functions and the analog pad. The VDDC is measured under the following conditions: Microcontroller in power down mode;RESET = VDDP; XTAL2 = VSSC; XTAL1 = N.C.; VAGND= VSSP; VAREF= VDDP; RxD/INT0 = VDDP; all other pins are set to input and connected to gnd; ALE output disabled and connected to gnd; 20mA current sourced from the VDDC pin.
2)
3)
4)
Ceramic type (20%) max ESR: 25m ,max trace length to capacitor is 10mm.
Data Sheet
70
V 1.0, 2003-05
C868
Power Supply Current Parameter Active mode C868-1S Symbol 40 IDDP MHz3) Limit Values typ. 13.1 13.5 7.8 7.9 3.5 3.6 3.4 3.6 240 240 240 240
Note:
1)
Unit Test Condition mA mA mA mA mA mA mA mA uA uA uA uA SAF-C868...8) SAK-C868...8) SAF-C868...8) SAK-C868...8)
7) 6) 5) 4)
1)
max. 15.6 15.5 9.6 9.1 4.4 4.1 4.2 4.1 300 400 300 400
2)
C868-1R 40 IDDP MHz3) Idle mode C868-1S
IDDP 40 MHz3)
C868-1R 40 IDDP MHz3) Active mode with slow-down enabled Idle mode with slowdown enabled C868-1S
IDDP 40 MHz3)
C868-1R 40 IDDP MHz3) C868-1S
IDDP 40 MHz3)
C868-1R 40 IDDP MHz3)
PowerC868-1S down mode C868-1R
IPDP IPDP
The typical IDDP values are periodically measured at TA = + 25 C but not 100% tested. The maximum IDDP values are measured under worst case conditions (TA = - 40 C and VDDP = 3.6 V). System clock, set by using external clock of 10.67MHz and setting KDIV in CMCON to 010 (factor of 4)
2)
3)
4)
IDDP (active mode) is measured with: XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP - 0.5 V; XTAL1 = N.C.; RESET = VDDP; all other pins are disconnected. ?IDDP would be slightly higher if the crystal oscillator is used (approx. 1 mA).
Data Sheet
71
V 1.0, 2003-05
C868
5)
IDDP (idle mode) is measured with all output pins disconnected and with all peripheral disabled: XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP - 0.5 V; XTAL1 = N.C.; RESET = VDDP; all other pins are disconnected.
6)
IDDP (active mode with slow down mode) is measured with all output pins disconnected: XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP - 0.5 V; XTAL1 = N.C.; RESET = VDDP; all other pins are disconnected; the microcontroller is put into slow-down mode by software with the slow-down clock set to 1/32 of system clock.
7)
IDDP (idle mode with slow down mode) is measured with all output pins disconnected and with all peripheral disabled: XTAL2 driven with tR, tF = 5 ns, VIL1,VIL2 = VSSP + 0.5 V, VIH1,VIH2 = VDDP - 0.5 V; XTAL1 = N.C.; RESET = VDDP; all other pins are disconnected; the microcontroller is put into slow-down mode by software with the slow-down clock set to 1/32 of system clock.
8)
IPDC and IPDP (power-down mode) are measured under the following conditions: RESET = VDDP; XTAL2 = VSSC; XTAL1 = N.C.; VAGND= VSSP; VAREF= VDDP; RxD/INT0 = VDDP; all other pins are set to input and connected to gnd; ALE output disabled and connected to gnd.
Data Sheet
72
V 1.0, 2003-05
C868
Power Supply Current Calculation Formulae Parameter Active mode C868-1S C868-1R Idle mode C868-1S C868-1R Active mode with slow-down enabled C868-1S C868-1R Idle mode with slowdown enabled C868-1S C868-1R
1)
Symbol
Formula1) 0.25* fSYS + 3.1 0.26 * fSYS + 5.2 0.27* fSYS + 2.7 0.29 * fSYS + 3.9 0.13* fSYS + 2.6 0.13 * fSYS + 4.0 0.13* fSYS + 3.7 0.15 * fSYS + 3.1 0.01 * fSYS + 3.1 0.02 * fSYS + 3.6 0.01 * fSYS + 3.2 0.01 * fSYS + 3.7 0.01* fSYS + 3.0 0.01 * fSYS + 3.8 0.02* fSYS + 2.8 0.02 * fSYS + 3.3
IDDPtyp IDDPmax IDDPtyp IDDPmax IDDPtyp IDDPmax IDDPtyp IDDPmax IDDPtyp IDDPmax IDDPtyp IDDPmax IDDPtyp IDDPmax IDDPtyp IDDPmax
fSYS is in MHz and results in mA.
Data Sheet
73
V 1.0, 2003-05
C868
A/D Converter Characteristics (Operating Condition Parameters) Parameter Analog input voltage Sample time Symbol Limits min max Unit Test Condition V
1)
VAIN tS
VAGND
64*tSYS 52*tSYS 48*tSYS 40*tSYS 32*tSYS 24*tSYS 16*tSYS 8*tSYS 322*tSYS 282*tSYS 242*tSYS 202*tSYS 162*tSYS 122*tSYS 82*tSYS 42*tSYS - - - -
VAREF
512*tSYS ns 448*tSYS 384*tSYS 320*tSYS 256*tSYS 192*tSYS 128*tSYS 64*tSYS 770*tSYS ns 674*tSYS 578*tSYS 482*tSYS 386*tSYS 290*tSYS 194*tSYS 98*tSYS 2 3 1.5 10 40
Prescaler/32 Prescaler/28 Prescaler/24 Prescaler/20 Prescaler/16 Prescaler/12 Prescaler/8 Prescaler/4 Prescaler/32 Prescaler/28 Prescaler/24 Prescaler/20 Prescaler/16 Prescaler/12 Prescaler/8 Prescaler/4
Conversion cycle time
tADCC
Total unadjusted error ADC input resistance
TUE RAIN
LSB VAGND VAIN VAREF2) VAGND VAIN VAREF3) k pF pF
4)5) 5) 5)
ADC input capacitance CAIN ADC reference pin CAREF capacitance Note:
1)
VAIN may exceed VAGND or VAREF up to the maximum ratings. However, the conversion result in these cases will be 00H or FFH, respectively.
TUE (max.) is tested at - 20 TA 125 C; VDDP = 3.3 V; VAREF = VDDP V and VSSP = VAGND. It is guaranteed by design characterization for all other voltages within the defined voltage range. TUE (max.) is tested at - 40 TA < - 20 C; VDDP 3.3 V; VAREF = VDDP and VSSP = VAGND. It is guaranteed
by design characterization for all other voltages within the defined voltage range.
2)
3)
Data Sheet
74
V 1.0, 2003-05
C868
4)
During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Not 100% tested, but guaranteed by design characterization.
5)
Data Sheet
75
V 1.0, 2003-05
C868
Clock calculation table for ADC TVC1) STC2) tADCC tS TVC1) STC2) tADCC tS TVC1) STC2) tADCC tS TVC1) STC2) tADCC tS TVC1) STC2) tADCC tS TVC1) STC2) tADCC tS 2 122 24 4 146 48 6 170 72 8 194 96 2 162 32 4 194 64 6 226 96 8 258 128 2 202 40 4 242 80 6 282 120 8 322 160 2 242 48 4 290 96 6 338 144 8 386 192 2 282 56 4 338 112 6 394 168 8 450 224 2 322 64 4 386 128 6 450 192 8 514 256 32 10 578 320 28 10 506 280 24 10 434 240 20 10 362 200 16 10 290 160 12 10 218 120 12 242 144 14 266 168 16 290 192 12 322 192 14 354 224 16 386 256 12 402 240 14 442 280 16 482 320 12 482 288 14 530 336 16 578 384 12 562 336 14 618 392 16 674 448 12 642 384 14 706 448 16 770 512
tADC3) tSYS tSYS
tADC3) tSYS tSYS
tADC3) tSYS tSYS
tADC3) tSYS tSYS
tADC3) tSYS tSYS
tADC3) tSYS tSYS
Data Sheet
76
V 1.0, 2003-05
C868
TVC1) STC2) tADCC tS TVC1) STC2) tADCC tS
1) 2) 3)
8 2 82 16 4 98 32 6 114 48 8 130 64 10 146 80 4 2 42 8 4 50 16 6 58 24 8 66 32 10 74 40 12 82 48 14 90 56 16 98 64 12 162 96 14 178 112 16 194 128
tADC3) tSYS tSYS
tADC3) tSYS tSYS
TVC is the clock divider specified by bit fields ADCTC. STC is the sample time control specified by bit fields ADSTC.
tADC is tSYS*TVC
Data Sheet
77
V 1.0, 2003-05
C868
AC Characteristics (Operating Condition Apply) External Clock Drive Characteristics Parameter Symbol Limit Values Variable Ext Clock 6.67 to 10.67 MHz min Oscillating period High time Low time Rise time Fall time ALE Characteristics Parameter Symbol Limit Values System freq = 6.25MHz to 40MHz Duty Cycle 0.5 min ALE pulse width ALE period max 320 960 ns ns Unit max 150 75 75 10 10 ns ns ns ns ns Unit
tOSC t1 t2 tR tF
93.75 46.875 46.875 -
tAWD tACY
50 150
Data Sheet
78
V 1.0, 2003-05
C868
t1
tR
tF
0.7 VDD c 0.2 VDDc 0.1 -
t2 tOSC
MCT04105
Figure 30
External Clock Drive on XTAL2
tAWD
tACY
Figure 31
ALE Characteristic
Data Sheet
79
V 1.0, 2003-05
C868
Package Outlines
Plastic Package, P-DSO-28-1 for SAF-C868-1RG BA, SAF-C868-1SG BA SAF-C868A-1RG BA, SAF-C868A-1SG BA and SAF-C868P-1SG BA, SAK-C868-1RG BA, SAK-C868-1SG BA, SAK-C868A-1RG BA, SAK-C868A-1SG BA and SAK-C868P-1SG BA.
0.2 -0.1 2.65 MAX.
0.35 x 45
8 MAX.
2.45 -0.2
7.6 -0.2 1)
1.27 0.35 +0.15 2)
0.1 0.2 28x
15
0.4 +0.8 10.3 0.3
28
1 Index Marking
1) 2)
18.1 -0.4
1)
14
Does not include plastic or metal protrusion of 0.15 max. per side Does not include dambar protrusion of 0.05 max. per side
Figure 32
DSO-28-1 Package Outlines
Data Sheet
80
0.23 +0.09
V 1.0, 2003-05
C868
Plastic Package, P-TSSOP-38-1 for SAF-C868-1RR BA, SAF-C868-1SR BA, SAF-C868A-1RR BA, SAF-C868A-1SR BA, SAF-C868P-1SR BA, SAK-C868-1RR BA, SAK-C868-1SR BA, SAK-C868A-1RR BA, SAK-C868A-1SR BA, and SAK-C868P-1SR BA.
4.4 0.1 3) B
0.125 +0.075 -0.0
0.1
6.4
1.2 MAX.
0.1 0.05
1 +0.05 -0.2
35
0.5 0.2 +0.07 2) -0.03
C 0.08 20
M
A C 38x
0.6 0.15
38
0.2 B 38x
1
19 9.7 0.1 1) A
Index Marking
1) 2) 3)
Does not include plastic or metal protrusion of 0.15 max. per side Does not include dambar protrusion of 0.08 max. per side Does not include plastic or metal protrusion of 0.25 max. per side
Figure 33
TSSOP-38-1 Package Outlines
Data Sheet
81
0...8
V 1.0, 2003-05
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Published by Infineon Technologies AG

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